vishay siliconix dg2303 document number: 72073 s-70852-rev. b, 30-apr-07 www.vishay.com 1 high-speed, low r on , 1.8-v/2.5-v/3.3-v/5-v, spst analog switch (1-bit bus switch) features ? sc-70 5-lead package ?5 switch connection between two ports ? minimal propagation delay through the switch ? low i cc ? zero bounce in flow-through mode ? control inputs compatible with ttl level description the dg2303 is a high-speed, 1-bit, low power, ttl- compatible bus switch. using sub-micron cmos technology, dg2303 achieves low on-resistance and negligible propagation delay. the dg2303 consist of a bi-dir ectional input/output pins a and b. when the output enable (o e) is low, the input/output pins are connected. when the oe is high, the switch is open and a high-impedance state exists between input/output pins a and b. functional block diagram and pin configuration * pb containing terminations are not rohs compliant, exemptions may apply v+ oe 1 2 3 5 top view a b gnd 4 sc-70 device markin g : e6 truth table oe b function l hiz state disconnect h a connect ordering information temp range package part number - 40 to 85 c sc70-5 dg2303dl-t1 DG2303DL-T1-E3 available pb-free rohs* compliant
www.vishay.com 2 document number: 72073 s-70852-rev. b, 30-apr-07 vishay siliconix dg2303 notes: a. signals on a, or b or oe exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum current rat ings. b. all leads welded or soldered to pc board. c. derate 3.1 mw/c above 70 c. absolute maximum ratings parameter limit unit reference v+ to gnd - 0.3 to + 6 v v oe, a, b a - 0.3 to (v+ + 0.3 v) continuous current (any terminal) 50 ma peak current (pulsed at 1 ms, 10 % duty cycle) 200 storage temperature (d suffix) - 65 to 150 c power dissipation (packages) b 5-pin sc70 c 250 mw specifications (v+ = 5.0 v) parameter symbol test conditions otherwise unless specified v+ = 1.65 v to 5.5 v, v in = v ih or v il e temp a limits - 40 to 85 c unit min b typ c max b dc characteristics on-resistance r on v+ = 1.8 v, v a = 0 v, i b = 4 ma full 28.0 v+ = 1.8 v, v a = 1.8 v, i b = 4 ma full 60.0 v+ = 2.3 v, v a = 0 v, i b = 8 ma full 12.0 v+ = 2.3 v, v a = 2.3 v, i b = 8 ma full 30.0 v+ = 3.0 v, v a = 0 v, i b = 24 ma full 9.0 v+ = 3.0 v, v a = 3.0 v, i b = 24 ma full 20.0 v+ = 4.5 v, v a = 0 v, i b = 30 ma full 7.0 v+ = 4.5 v, v a = 2.4 v, i b = 15 ma full 12.0 v+ = 4.5 v, v a = 4.5 v, i b = 30 ma full 15.0 r on flatness d r on flatness v+ = 1.8 v, v a = 0 v to v+, i b = 4 ma full 125 v+ = 2.5 v, v a = 0 v to v+, i b = 8 ma full 28 v+ = 3.3 v, v a = 0 v to v+, i b = 24 ma full 12 v+ = 5.0 v, v a = 0 v to v+, i b = 30 ma full 6 switch off leakage current i (off) v+ = 5.5 v, v a = 1 v/4.5 v, v b = 4.5 v/1 v full - 10 10 a switch-on leakage current i (on) v+ = 5.5 v, v a = v b = 1 v/4.5 v full - 10 10 input high voltage v ih v+ = 1.65 v to 1.95 v full 1.35 v v+ = 2.3 v to 2.7 v full 1.6 v+ = 3.0 v to 3.6 v full 2.0 v+ = 4.5 v to 5.5 v full 2.4 input low voltage v il v+ = 1.65 v to 1.95 v full 0.4 v+ = 2.3 v to 2.7 v full 0.4 v+ = 3.0 v to 3.6 v full 0.6 v+ = 4.5 v to 5.5 v full 0.8 input current i il or i ih v oe = 0 or v+ full - 1 1 a
document number: 72073 s-70852-rev. b, 30-apr-07 www.vishay.com 3 vishay siliconix dg2303 notes: a. room = 25 c, full = as determined by the operating suffix. b. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by design and not production te sted. the bus switch propagation delay is a function of the rc time constant cont ributed by the on-resistance and the specified load capacit ance with an ideal voltage source (zer o output impedance) driving the switch. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications parameter symbol test conditions otherwise unless specified v+ = 1.65 v to 5.5 v, v in = v ih or v il e temp a limits - 40 to 85 c unit min b typ c max b dynamic characteristics prop delay bus-to-bus f t phl , t plh v ld = open, v = 1.65 v to 1.95 v, (figure 1 and 2) full 5 ns v ld = open, v = 2.3 v to 2.7 v, (figure 1 and 2) full 2 v ld = open, v = 3.0 v to 3.6 v, (figure 1 and 2) full 1 v ld = open, v = 4.5 v to 5.5 v, (figure 1 and 2) full 1 output enable time d t pzl v ld = 2 x v+, v+ = 1.65 v to 1.95 v (figure 1 and 2) full 4.2 v ld = 2 x v+, v+ = 2.3 v to 2.7 v (figure 1 and 2) full 3.3 v ld = 2 x v+, v+ = 3.0 v to 3.6 v (figure 1 and 2) full 2.6 v ld = 2 x v+, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 1.8 t pzh v ld = 0 v, v+ = 1.65 v to 1.95 v (figure 1 and 2) full 4.4 v ld = 0 v, v+ = 2.3 v to 2.7 v (figure 1 and 2) full 3.3 v ld = 0 v, v+ = 3.0 v to 3.6 v (figure 1 and 2) full 2.7 v ld = 0 v, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 2.0 output disable time d t plz v ld = 2 x v+, v+ = 1.65 v to 1.95 v (figure 1 and 2) full 14.3 v ld = 2 x v+, v+ = 2.3 v to 2.7 v (figure 1 and 2) full 10.5 v ld = 2 x v+, v+ = 3.0 v to 3.6 v (figure 1 and 2) full 8.6 v ld = 2 x v+, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 7.4 t phz v ld = 0 v, v+ = 1.65 v to 1.95 v (figure 1 and 2) full 10.7 v ld = 0 v, v+ = 2.3 v to 2.7 v (figure 1 and 2) full 9.6 v ld = 0 v, v+ = 3.0 v to 3.6 v (figure 1 and 2) full 8.7 v ld = 0 v, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 7.5 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 , (figure 3) room 0.5 pc off isolation d oirr r l = 50 , c l = 5 pf, f = 10 mhz room - 50 db insertion loss d loss r l = 50 room > 200 mhz input capacitance d c in room 4 pf channel-off capacitance d c (off) v oe = 0 or v+, f = 1 mhz room 9 channel-on capacitance d c on room 20 power supply power supply range v+ 1.65 5.5 v power supply current i+ v oe = 0 or v+ 1.0 a
www.vishay.com 4 document number: 72073 s-70852-rev. b, 30-apr-07 vishay siliconix dg2303 ac loading and waveforms figure 1. ac test circuit oe logic input switch input ab v ld r a = 500 r b = 500 c l c l = 50 pf switch outpu t input driven by 50 source terminated in 50 c l includes load and stray capacitance input prr = 1.0 mhz, t w = 50 ns figure 2. ac waveforms t r = 2.5 ns t f = 2.5 ns t f = 2.5 ns t r = 2.5 ns v+ v+ gnd gnd logic input switch input 10 % 10 % 10 % 10 % 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 90 % 90 % 90 % 90 % t w output output output t plh t phl v oh v ol t pzl t plz t pzh t phz 1.5 v v ol + 0.3 v v ol v oh v oh - 0.3 v v ld 2 0 v
document number: 72073 s-70852-rev. b, 30-apr-07 www.vishay.com 5 vishay siliconix dg2303 test circuits vishay siliconix maintains worldwide manufac turing capability. products ma y be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?72073. figure 3. charge injection off on on in v out v out q = v out x c l c l = 0.1 nf b r gen v out a v in = 0 - v+ oe v gen gnd v+ v+ in depends on switch configuration: input polarity determined b y sense of switch. + figure 4. off-isolation oe gnd a v in 10 nf b off isolation 20 log v b v a r l analyzer v+ v+ = figure 5. channel off/on capacitance a f = 1 mhz oe b gnd vin meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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